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CXA3197R
10-bit 125MSPS D/A Converter
Description The CXA3197R is a high-speed D/A converter which can perform multiplexed input of two system 10-bit data. This IC realizes a maximum conversion rate of 125MSPS. Multiplexed operation is possible by inputing the 1/2 frequency-divided clock or by halving the frequency of the clock internally with the clock frequency divider circuit having the reset pin. The data input is at TTL level, and the clock input and reset input can select either TTL or PECL level according to the application. Features * Maximum conversion rate: During PECL operation: 125MSPS During TTL operation: 100MSPS * Resolution: 10 bits * Low power consumption: 480mW (typ.) * Data input level: TTL * Clock, reset input level: TTL and PECL compatible * 2:1 multiplexed input function * 1/2 frequency-divided clock output possible by the built-in clock frequency divider circuit * Voltage output (50 load drive possible) * Single power supply or dual power supply operation * Reset signal polarity switching function
AGND2 AOUTP AOUTN
48 pin LQFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic IC Applications * LCD * DDS * HDTV * Communications (QPSK, QAM) * Measuring devices
36 35 34 33 32 31 30 29 28 27 26 25 AGND2 37 VOCLP 38 R POLARITY 39 INV 40 PS 41 DVCC1 42 N.C. 43 DGND1 44 (MSB) DA9 45 DA8 46 DA7 47 DA6 48 1 2 3 4 5 6 7 8 9 10 11 12 24 RESETN/E 23 RESETP/E 22 RESET/T 21 CLKN/E 20 CLKP/E 19 CLK/T 18 DIV2OUT
C1
DGND2
17 DIV2IN 16 DB0 (LSB) 15 DB1 14 DB2 13 DB3
Pin Configuration
AVCC2 VSET VREF
AVCCO
DVCC2
C3 DB7
DA3
DA2
DA4
(MSB) DB9
DA5
DB8
DB6
C2
(LSB) DA0
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
DA1
-1-
DB5
DB4
E97639-PS
CXA3197R
Absolute Maximum Ratings (Ta = 25C) * Supply voltage AVCCO, AVCC2, DVCC2 AGND2, DGND2 DVCC1 AVCC2 - AGND2 AVCCO - AGND2 DVCC2 - DGND2 -0.5 to +6.0 -6.0 to +0.5 -0.5 to +6.0 -0.5 to +6.0 -0.5 to +6.0 -0.5 to +6.0 V V V V V V
* Input voltage (Analog) (Digital)
VSET AGND2 - 0.5 to AVCC2 + 0.5 V TTL input pin DGND1 - 0.5 to DVCC1 + 0.5 V PECL input pin DGND1 - 0.5 to DVCC1 + 0.5 V PS DGND1 - 0.5 to DVCC1 + 0.5 V (Others) VOCLP DGND1 - 0.5 to DVCC1 + 0.5 V * Storage temperature Tstg - 65 to +150 C * Allowable power dissipation Pd 1.4 W (when mounted on a two-layer glass fabric base epoxy board with dimensions of 76mm x 114mm, t = 1.6mm)
Recommended Operating Conditions [Single power supply] * Supply voltage Min. Typ. Max. AVCCO +4.75 +5.0 +5.25 AVCC2 +4.75 +5.0 +5.25 AGND2 -0.05 0.0 +0.05 DVCC1 +4.75 +5.0 +5.25 DGND1 -0.05 0.0 +0.05 DVCC2 +4.75 +5.0 +5.25 DGND2 -0.05 0.0 +0.05 * Input voltage (Analog) (Digital) VSET TTL input pin
[Dual power supply] Min. Typ. Max. -0.05 0.0 +0.05 -0.05 0.0 +0.05 -5.50 -5.0 -4.75 +4.75 +5.0 +5.25 -0.05 0.0 +0.05 -0.05 0.0 +0.05 -5.50 -5.0 -4.75 Typ.
Unit V V V V V V V Max. Unit AGND2 + 1.03 V V DGND1 + 0.8 V DVCC1 - 0.5 V DVCC1 - 1.4 V V DVCC1 V ns ns MSPS MSPS 10k 2.1 1.05 +75 V V C
* * * * *
Min. AGND2 + 0.65 VIH DGND1 + 2.0 VIL PECL input pin VIH DVCC1 - 1.05 VIL DVCC1 - 3.2 VID1 0.5 (Others) VOCLP DGND1 + 2.4 CLK pulse width (for RECL CLK) tpw1 3.5 tpw0 3.5 Maximum conversion rate During PECL operation Fc 125 During TTL operation Fc 100 Load resistance RL 50 Analog output full-scale voltage VFS 1.5 RL 10k RL = 50 VFS 0.75 Operating temperature Ta -20
0.8
50 2.0 1.0
1 VID: Input Voltage Differential PECL input signal switching level
DVCC1 VIH (Max.) VIL VID VIH VIL (Min.) DGND1
-2-
CXA3197R
Pin Description [Symbol] DA0 to DA9 DB0 to DB9 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 C1 C2 C3 DVCC2 AVCCO AOUTN AOUTP AGND2 VREF VSET [Pin No.] 1 to 6, 45 to 48 7 to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 [Description]
[
Typical voltage level for a single power supply
][
Typical voltage level for dual power supply TTL TTL TTL TTL TTL PECL PECL TTL PECL PECL -5V TTL TTL TTL 0V 0V (typ.) AVCCO - VFS AVCCO - VFS -5V AGND2 + 1.25V AGND2 + 0.65V to AGND2 + 1.03V 0V -5V Clamp voltage TTL TTL TTL 5V -- 0V
]
Side A data input. TTL Side B data input. TTL 1/2 frequency-divided clock input. TTL 1/2 frequency-divided clock output. TTL TTL clock input. TTL PECL clock input. PECL PECL clock input. PECL TTL reset input. TTL PECL reset input. PECL PECL reset input. PECL Digital ground. 0V Function setting. TTL Function setting. TTL Function setting. TTL Digital power supply. 5V Analog output power supply. 5V (typ.) Negative analog output. AVCCO - VFS Positive analog output. AVCCO - VFS Analog ground. 0V Analog reference voltage. AGND2 + 1.25V Full-scale adjustment. AGND2 + 0.65V to AGND2 + 1.03V Analog power supply. Analog ground. TTL High level clamp. Reset signal polarity switching. Analog output inversion. Power saving. Digital power supply. Not connected. Digital ground. 5V 0V Clamp voltage TTL TTL TTL 5V -- 0V
AVCC2 AGND2 VOCLP R POLARITY INV PS DVCC1 N.C. DGND1
36 37 38 39 40 41 42 43 44
-3-
CXA3197R
Block Diagram
DVCC1 42
DVCC2 29
VOCLP 38
INV 40
PS 41
36 AVCC2
DA0 to DA9
1 to 6 45 to 48
10bit
Input Latch A
10bit RO = 50 10bit MUX Latch 10bit
30 AVCCO 32 AOUTP
31 AOUTN 10bit DB0 to DB9 7 to 16 Input Latch B 10bit AGND2 DIV2OUT 18
Current Cont. D Q Q BGR 34 VREF
DIV2IN 17
CLK/T 19 CLKP/E 20 CLKN/E 21 RESET/T 22 RESETP/E 23 RESETN/E 24 R POLARITY 39 33 37 AGND2 35 VSET
44 DGND1
25 DGND2
26 C1
27 C2
28 C3
-4-
CXA3197R
Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O Typical voltage level Equivalent circuit Description
1 to 6 45 to 48
DA0 to DA9
I
TTL
1
DVCC1
Side A data input.
to 6
45 to 48 7 to 16 DGND1 1.5V
7 to 16
DB0 to DB9
I
TTL
Side B data input.
DVCC1
17
DIV2IN
I
TTL
17 1.5V DGND1
1/2 frequency-divided clock input. Use this pin in MUX.1A or MUX.2 mode. Leave open for other modes.
DVCC1
18
DIV2OUT
O
TTL
100K
18
DGND1
1/2 frequency-divided clock output. The 1/2 frequencydivided clock signal (DIV2OUT) is output in MUX.1A mode. Set to high impedance for other modes.
DVCC1
19
CLK/T
I
TTL
19 1.5V DGND1
Clock input. Use this pin when the clock is input at TTL level. At this time, leave Pins 20 and 21 open.
-5-
CXA3197R
Pin No.
Symbol
I/O Typical voltage level
Equivalent circuit
Description Clock input. Use this pin when the clock is input at PECL level. At this time, leave Pin 19 open. CLKP/E and CLKN/E are complementary and should be used together. CLKP/E complementary input. Reset signal input. When multiple CXA3197R are operated at the same time in MUX.1A or MUX.1B mode, the start timing of the internal 1/2 frequency divider circuits should be matched. At this time, the reset signal is used; when the reset signal is at TTL level, Pin 22 is used and Pins 23 and 24 are left open. When the reset signal is at PECL level, Pins 23 and 24 are used and Pin 22 is left open. The reset signal polarity can be set by Pin 39 (R POLARITY). Leave the reset pin open when other modes are used. RESETP/E and RESETN/E are complementary and should be used together.
DVCC1
20
CLKP/E
I
PECL
20 21
DGND1
21
CLKN/E
I
PECL
DVCC1
22
RESET/T
I
TTL
22 1.5V DGND1
23
RESETP/E
I
PECL
DVCC1
23 24
24
RESETN/E
I
PECL
DGND1
25
DGND2
Single power supply: GND Dual power supply: -5V I TTL
DVCC1
Digital power supply.
26
C1
Function setting.
27
C2
I
TTL
26 27 28 1.5V
Function setting.
28
C3
I
TTL
DGND1
Function setting. -6-
CXA3197R
Pin No.
Symbol
I/O Typical voltage level Single power supply: +5V Dual power supply: GND
Equivalent circuit
Description
29
DVCC2
Digital power supply.
30
AVCCO
Single power supply: +5V Dual power supply: GND
Analog output power supply. The AVCCO pin voltage can be varied within the range that satisfies the analog output compliance voltage. Negative analog output. The inverse of the positive analog output pin is output. When the positive output is terminated with 50, the inverse output pin should also be terminated with 50 even if the inverse output is not used. Positive analog output.
AVCCO RO RO 31
31
AOUTN
O
AVCCO - VFS
32
AGND2
32
AOUTP
O
AVCCO - VFS Single power supply: GND Dual power supply: -5V
AVCC2
33
AGND2
Analog ground.
34
VREF
O
AGND + 1.25V (Typ.)
BGR
34
Reference voltage output.
AGND2
AVCC2
35
VSET
I
AGND2 + 0.65V to AGND2 + 1.03V
35
Analog output full-scale adjustment.
AGND2
36
AVCC2
Single power supply: +5V Dual power supply: GND -7-
Analog power supply.
CXA3197R
Pin No.
Symbol
I/O Typical voltage level Single power supply: GND Dual power supply: -5V
Equivalent circuit
Description
37
AGND2
Analog power supply.
DVCC1
38
VOCLP
I
Clamp voltage
38
DGND1
TTL output High level clamp. A TTL level signal is output from the DIV2OUT pin in MUX.1A mode. The TTL High level voltage can be clamped to the value approximately equivalent to the voltage applied to this pin. Leave the VOCLP pin open for other modes.
DVCC1
39
R POLARITY
I
TTL
39 1.5V DGND1
Reset signal polarity switching. At High level, the reset polarity is active Low; at Low level, active High.
DVCC1
40
INV
I
TTL
40 1.5V DGND1
Analog output polarity inversion. The analog output is inverted at Low level.
DVCC1
41
41
PS
I
TTL
Power saving. Power saving mode is activated at Low level. Normally pull up the PS pin to High level as this pin is open Low.
DGND1
42 43 44
DVCC1 N.C. DGND1
5V
Digital power supply. Not connected.
0V
Digital ground.
-8-
CXA3197R
Electrical Characteristics (DVCC1, DVCC2, AVCC2, AVCCO = +5V, DGND1, DGND2 = 0V, Ta = 25C) Item Resolution Differential linearity error Integral linearity error Digital input (PECL) Digital input voltage Digital input current Digital input capacitance Digital input (TTL) Digital input voltage Threshold voltage Digital input current Digital input capacitance Digital output (TTL) Digital output voltage Leak current at high impedance Digital output rise time Digital output fall time PS pin input (PS) PS pin input voltage PS pin input current Clamp pin (VOCLP) VOCLP pin input current Analog output characteristics Output full-scale voltage : RL 10k : RL = 50 Output zero offset voltage : RL 10k : RL = 50 Analog output resistance Analog output capacitance Absolute amplitude error Absolute amplitude error temperature characteristics Analog output rise time Analog output fall time Settling time Glitch energy Compliance voltage Tr Tf VIH VIL IIH IIL IVOCLP IVOCLP VOH VOL IOH = -2.0mA IOL = 1.0mA When VO = 5V When VO = 0V 0.8 to 2.4V (CL = 10pF) 0.8 to 2.4V (CL = 10pF) 2.4 10 -1 1 0.6 2 VIH = 3.5V VIL = 0.2V VOCLP = DVCC1 VOCLP = 2.4V 1 -1 0 -60 0.8 100 0 5 -10 0.5 100 1 1.5 1.2 VIH VIL VTH IIH IIL 2 0.8 1.5 VIH = 3.5V VIL = 0.2V -1 -2 1 0 5 Symbol n DLE ILE VIH VIL IIH IIL DVCC1 - 1.05 DVCC1 - 3.2 0 -30 VFS = 1000mV 2 Conditions Min. 10 Typ. 10 Max. 10 -0.85/+0.5 -1.2/+0.5 1.2 DVCC1 - 0.5 DVCC1 - 1.4 20 0 5 Unit bit LSB LSB LSB V V A A pF V V V A A pF V V A A ns ns V V A A A A
VIH = DVCC1 - 0.8V VIL = DVCC1 - 1.6V
VFS VFS VOF VOF RO CO EG TCG Tr Tf
1.5 0.75
2 1
2.1 1.05 20 10
V V mV mV pF % of F.S. ppm/C ns ns ns pVsec V
} VSET = AGND2 + 937.5mV
VSET = AGND2 + 937.5mV VFS = 1000mV at 25C RL = } When 1V,1050, VFS = - 90% Mesured to DVCC2 3
0 0 50 10 -4.0 0.85 0.75 -2.1
4.0 60 1.05 0.85 3.5 5 1.5
tSET
GE VOC
-9-
CXA3197R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Reference/control amplifier characteristics VREF pin output voltage VREF VREF pin output voltage VREF in PS mode VREF voltage drift coefficient ISET VSET pin input current Multiplying bandwidth Current consumption ICC DICC1 DICC2 AICC2 AICCO Current consumption in PS ICC mode 4 DICC1
} IREFOUT = 1mA
100mVp-p, SIN, at -3dB Total current consumption DIcc1 current consumption DIcc2 current consumption AIcc2 current consumption AIccO current consumption Total current consumption in PS mode DIcc1 current consumption in PS mode DIcc2 current consumption in PS mode AIcc2 current consumption in PS mode AIccO current consumption in PS mode
AGND2 + 1.18 AGND2 + 1.25 AGND2 + 1.32 AGND2 + 1.18 AGND2 + 1.25 AGND2 + 1.32 250 -5 50 63 7 13 6 37 96 15.5 19 8.5 53 0.432 0
V V ppm/C A MHz mA mA mA mA mA mA
129 24 25 11 69 4
0.38
1.5
mA
DICC2
0.001
0.2
mA
AICC2
0.05
0.3
mA
AICCO
0.001
2
mA
2 64-step D.L.E.
This indicates the D.L.E. when the INV pin is High and the data input code changes between: (MSB) (LSB) (MSB) (LSB) 0001000000 0000111111 at the AOUTP side output or between: (MSB) (LSB) (MSB) (LSB) 1110111111 1111000000 at the AOUTN side output.
3 When using the analog output within the compliance voltage range, set AVCCO so that it satisfies the following equations. VOC (min) = (AVCCO - VFS) - DVCC2 -2.1V VOC (max) = (AVCCO - VOF) - DVCC2 1.5V
- 10 -
CXA3197R
4 The current consumption in power saving mode does not include the VREF pin output current. When grounding the VREF pin to the AGND2 level using external resistance, a voltage of 1.18 to 1.32V is generated at the VREF pin even in power saving mode. Therefore, the current indicated by the following equation flows from the AVCC2 pin to the VREF pin. This value must be added to obtain the actual current consumption in power saving mode. VREF pin voltage = IREFOUT External resistance
AVCC2
BGR 34 VREF In power saving mode: IREFOUT = VREF pin voltage External resistance
AGND2
- 11 -
CLK signal level PECL TTL TTL Max. 100 125 3.5 3.5 4.0 0 9.5 12.0 2T - 7 1.0 5.0 4 5 5.0 125 3.5 3.5 0 1.0 1.0 4.0 2 3 5.0 5.5 6.0 6.5 5.5 6.0 6.5 100 4.5 3.0 1.0 3.0 1.0 6.0 2 3 7.5 8.5 5.0 5 7.5 8.5 5.0 125 3.5 3.5 4.0 0 1.0 4.0 2 3 5.5 6.0 4 1.0 5.0 4 5 5.5 6.0 5.5 6.5 8 2T - 7 4.5 3.0 1.0 3.0 6.5 2T - 7 1.0 5.0 8 8.0 MSPS ns ns ns ns ns ns ns ns CLK ns MSPS ns ns ns ns ns ns CLK ns Min. Typ. Min. Typ. Max. Unit Max. TTL PECL PECL Reset signal level Symbol Conditions Min. Typ. FC 125 3.5 3.5 0 1.0 CL = 10pF 5.5 Tpw1 Tpw0 ts-rst th-rst td-DIV 2T-tm ts th tPD (A) tPD (B) tdo FC Tpw1 Tpw0 ts-rst th-rst ts th tPD (A) tPD (B) tdo
Item
Maximum conversion rate
Clock High pulse width
Clock Low pulse width
Reset signal setup time
Reset signal hold time
DIV2OUT output delay
DIV2OUT to DIV2IN maximum delay time
MUX.1A mode
Data input setup time
Data input hold time
Analog output pipeline delay
Switching characteristics
MUX.1B mode
- 12 -
Analog output delay
Maximum conversion rate
Clock High pulse width
Clock Low pulse width
Reset signal setup time
Reset signal hold time
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
CXA3197R
CLK signal level Reset signal level Symbol Conditions Min. Typ. 125 3.5 3.5 4.5 0 1.0 5.0 2 3 5.0 125 3.5 3.5 1.0 2.5 1.0 2.0 1 1 5.0 5.5 6.0 6.5 5.5 6.0 6.5 100 4.5 3.0 1.0 3.5 1.5 3.5 1 1 7.5 8.5 ns 3 7.5 8.5 ns MSPS ns ns ns ns ns ns CLK 2 5.0 1.0 3.5 ns ns ns CLK 2.0 ns 3.0 ns 4.5 ns 100 MSPS Max. Min. Typ. Max. FC Tpw1 Tpw0 ts-DIV th-DIV ts th tPD (A) tPD (B) tdo FC Tpw1 Tpw0 ts-C2 th-C2 ts th tPD (A) tPD (B) tdo Unit PECL -- 4 TTL -- 4
Item
Maximum conversion rate
Clock High pulse width
Clock Low pulse width
DIV2IN setup time
DIV2IN hold time
MUX.2 mode
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
Switching characteristics
SELE.A, SELE.B modes
- 13 -
Maximum conversion rate
Clock High pulse width
Clock Low pulse width
C2 signal setup time
C2 signal hold time
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
4 The reset signal is not input in MUX.2, SELE.A or SELE.B mode.
CXA3197R
CXA3197R
Electrical Characteristics Measurement Circuits Differential Linearity Error Integral Linearity Error
10 10-bit Data input 10 DA0 to DA9 DB0 to DB9 CLK/T 1MHz TTL CLK
+5V
DVCC1
DGND1 DVCC2 AVCC2 AVCCO AOUTP 50 AOUTN 50 VSET DGND2 AGND2 937.5mV -5V -5V
CXA3197R
DVM (Digital Voltmeter)
C1 C2 C3
PC
+5V
Current Consumption
+5V
I1
I2
I3
I4
DVCC1 DVCC2 AVCC2 AVCCO High for all side A data 10 10 DA0 to DA9 DB0 to DB9 CXA3197R CLK/T 1MHz TTL CLK +5 DIV2IN DIV2OUT PS C1 C2 C3 DGND1 DGND2 AGND2 VSET AOUTP
ICC = I1 + I2 + I3 + I4 DICC1 = I1 DICC2 = I2 AICC2 = I3 AICCO = I4
Low for all side B data
AOUTN
937.5mV
Analog Output Characteristics Output Full-Scale Absolute Amplitude Error Output Zero Offset Voltage
High for all side A data 10
+5V
DVCC1 DA0 to DA9 DB0 to DB9 CLK/T
DGND1 DVCC2 AVCC2 AOUTP AVCCO 50
Low for all side B data
10
CXA3197R AOUTN 50 VSET
1MHz TTL CLK
+5 INV C1 C2 C3
DGND2 AGND2
937.5mV -5V
-5V +5
- 14 -
CXA3197R
Analog Output Rise Time Analog Output Fall Time Settling Time Glitch Energy
Oscilloscope
+5V 50 50 DVCC1 D. P. G. (Digital Pattern Generator) 10 10 DA0 to DA9 DB0 to DB9 CLKP/E CLKN/E 100MHz PECL CLK VSET C1 C2 C3 DGND2 AGND2 -5V +5V -5V DGND1 DVCC2 AVCC2 AOUTP AVCCO AOUTN CXA3197R VREF
Reference/Control Amplifier Characteristics VREF Pin Output Voltage VREF Pin Output Voltage in Power Saving Mode Multiplying Bandwidth
Oscilloscope +5V
DVCC1 High for all side A data 10 10 DA0 to DA9 DB0 to DB9 CLKP/E CLKN/E 20MHz PECL CLK +5V
DGND1 DVCC2 AVCC2 AVCCO AOUTP
50
High for all side B data
AVCCO (= 0V) VFS 50 AOUTP output 0.1F 50 -5V VSET pin output 100mVp-p AGND2 + 937.5mV
AOUTN CXA3197R VREF 1mA VSET
PS C1 C2 C3
DGND2 AGND2
+5V
-5V
- 15 -
CXA3197R
AVCCO AVCCO - VOF
AOUTP output (INV = 1)
AVCCO - VFS
(AVCCO - VOF) - (AVCCO - VFS) 1023 V (n + 1) - V (n) -1 1LSB V (n) - n x 1LSB 1LSB
= 1LSB
D.L.E. =
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1 * * * * * * * * * * *
1 1 1
1 1 1
1 1 1
1 1 0
1 0 1
I.L.E. =
V (n + 1)
V (n)
0 0 0 0 0 D9 (MSB)
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 0 0 0 0
0 1 1 0 0
0 1 0 1 0 D0 (LSB)
Data input code
Data input code INV = 1 (MSB) D9 (LSB) D0 (MSB) D9 INV = 0 (LSB) D0
Analog output level AOUTP AVCCO - VOF : AVCCO - VFS AOUTN AVCCO - VFS : AVCCO - VOF
1111111111 : 0000000000
0000000000 : 1111111111 Table 1. I/O Correspondence Table
- 16 -
CXA3197R
Description of Operation The CXA3197R has four types of operation modes to support various applications. The operation mode is set by switching the function setting pins (C1, C2 and C3). Operation Mode Table Mode C1 C2 C3 0 0 1 0 1 0 1 0 0 125 SELE.B 1 0 High impedance 125 62.5 125 CLK IN Data IN AOUT (MSPS) (Mbps) (Mbps) DIV2OUT pin Outputs CLK/2 at TTL level High impedance High impedance High impedance Description of operation MUX operation by the internal CLK/2 MUX operation by the internal CLK/2 MUX operation by DIV2IN D/A conversion of side A data input D/A conversion of side B data input
MUX.1A 0 MUX.1B 0 MUX.2 0
SELE.A 1
The CXA3197R can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplex the data, and output it as an analog signal, making it possible to halve the data rate. This lets the CXA3197R support the TTL data input level in contrast to the ECL data input level for conventional high-speed D/A converters. The clock signal and reset signal input levels can be selected from either TTL or PECL according to the application. (However, setting both signals to either TTL or PECL input level is recommended.) 1. MUX.1A mode Set C1, C2 and C3 all Low for this mode. In MUX.1A mode, the frequency of the clock input from the clock input pin is halved internally, and the 1/2 frequency-divided signal is output at TTL level from the DIV2OUT pin. Data synchronized with the DIV2OUT signal (the signal output from the DIV2OUT pin) can be obtained by operating the CXA3197R front-end system with the DIV2OUT signal. The timing at which the data output delay of the CXA3197R front-end system matches with the hold time during CXA3197R data input can be easily set by inputting this synchronized data to the data input pins and the DIV2OUT signal to the DIV2IN pin. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplexed, and extracted as analog output.
Clock input pin Clock input 1/2 DIV2OUT pin (DIV2OUT signal) DIV2IN pin CXA3197R (MUX.1A mode)
td - DIV
10bit Data. A CXA3197R front-end system 10bit 10bit Data. B 10bit
DA0 to DA9
DB0 to DB9 Data input pins
Front-end system data output delay CXA3197R data input hold time
=
- 17 -
CXA3197R
When using the multiple CXA3197R in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See the timing chart for the detailed timing.
Example when not using the reset signal
CLK CXA3197R CLK CLK DIV2OUT DIV2OUT
CXA3197R CLK DIV2OUT DIV2OUT
Example when using the reset signal
CLK Reset signal (when active Low) DIV2OUT
CXA3197R CLK CLK DIV2OUT RESET CXA3197R CLK DIV2OUT Reset signal RESET
DIV2OUT
- 18 -
CXA3197R
2. MUX.1B mode Set C1 and C2 Low and C3 High for this mode. In MUX.1B mode, the frequency of the clock input from the clock input pin is halved internally, and the data is loaded by this 1/2 frequency-divided signal. The 1/2 frequency-divided signal cannot be observed at this time, so the data is actually loaded by observing the clock and reset signals to estimate the rising edge of the internally 1/2 frequency-divided signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay after loading by the clock.
Clock input pin Clock th-rst Reset signal (when active Low) Internally 1/2 frequency-divided signal (This signal cannot be observed.) DA0 to DA9 ts-rst Reset input pin
CXA3197R (MUX.1B mode) 1/2
ts
th
DB0 to DB9 Data input signal
After the reset is released, the internal 1/2 frequency-divided signal commences at the first clock edge, so be sure to input the data in a manner that satisfies the setup time (ts) and hold time (th) with respect to this clock edge.
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CXA3197R
Like MUX.1A mode, when using the multiple CXA3197R in MUX.1B mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example below. As a countermeasure, the MUX.1B mode also has a function that matches the start timing of the 1/2 frequency-divided clocks with the reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low; when Low, reset is active High. See the timing chart for the detailed timing.
Example when not using the reset signal
CLK CXA3197R CLK CLK Internally 1/2 frequency-divided signal
CXA3197R CLK
Internally 1/2 frequency-divided signal
Example when using the reset signal
CLK Reset signal (when active Low) Internally 1/2 frequency-divided signal
CXA3197R CLK CLK RESET CXA3197R CLK RESET signal RESET
Internally 1/2 frequency-divided signal
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CXA3197R
3. MUX.2 mode Set C1 and C3 Low and C2 High for this mode. In MUX.2 mode, the clock is input to the clock input pin, and the signal with a cycle half that of the clock (hereafter, DIV2IN signal) is input to the DIV2IN pin at TTL level. The DIV2IN signal is internally latched by the clock, so consideration must be given to the setup time (ts_DIV) and hold time (th_DIV) with respect to the clock. In addition, the data is loaded by the DIV2IN signal, so consideration must also be given to the setup time (ts) and hold time (th) with respect to the DIV2IN signal. The data can be divided and input to two systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3clock pipeline delay from the clock that loads the DIV2IN signal. See the timing chart for the detailed timing.
tPD (B) tPD (A) 0 Clock ts_DIV DIV2IN signal ts System A data A0 A1 th th_DIV 1 2 3
CXA3197R (MUX.2 mode) Clock input pin
DIV2IN input pin
DA0 to DA9 A2
DB0 to DB9 System B data B0 B1 B2
Analog output signal
A0
B0
A1
B1
- 21 -
CXA3197R
4. SELE.A mode and SELE.B mode Set C1 High and C2 and C3 Low for SELE.A mode. In SELE.A mode, the clock is input to the clock input pin, and the data is input to the system A (DA0 to DA9) data input pins. Set C1 and C2 High and C3 Low for SELE.B mode. In SELE.B mode, the clock is input to the clock input pin, and the data is input to the system B (DB0 to DB9) data input pins. In either mode, consideration must be given to the setup time (ts) and hold time (th) with respect to the clock. Also, the data is output as an analog signal with a 1-clock pipeline delay after loading by the clock. Switching between SELE.A mode and SELE.B mode is done by switching the C2 pin between High and Low levels. Also, the mode can be switched at high speed in sync with the clock by inputting the switching signal (C2 signal) to the C2 pin. The C2 signal is internally latched by the clock, so consideration must be given to the setup time (ts_C2) and hold time (th_C2) with respect to the clock. See the timing chart for the detailed timing.
tPD (A) 0 Clock 1
tPD (B) 0 1 ts_C2 th_C2
CXA3197R (SELE.A mode/SELE.B mode) Clock input pin
C2 input pin C2 signal ts th System A data A0 A1 A2 A6 A8 DA0 to DA9 Select System B data B3 B4 B5 B7 DB0 to DB9
Analog output signal A0
A1
A2
B3
B4
B5
A6
- 22 -
CXA3197R
Block Diagram & Timing Chart (MUX.1A Mode)
CLK RESET RQ DQ DIV2OUT DIV2IN Input Data A Input Latch A Latch MUX Input Data B Input Latch B Latch Latch DAC Analog out CLK/2 (Internal)
Tpw1 Tpw0 CLK ts-rst th-rst (Active High) (Active Low) td-DIV 0 1
tPD (B) tPD (A)
2
3
4
5
RESET
DIV2OUT tm DIV2IN 2T-tm Input Data A Input Data B N$ N$ N$ N$ ts N N +1 th N+2 N+3 N+4 N+5
tdo N$ N$ N
N+1 tdo
N$
N$
In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be output at TTL level (DIV2OUT). CLK/2 can be reset by the reset signal.
(Timing judgment points)
PECL
CLK
1/2LSB
TTL
2.0V 0.8V
2.0V 0.8V
Analog output
1/2LSB
tdo
tSET
- 23 -
CXA3197R
Block Diagram & Timing Chart (MUX.1B Mode)
CLK RESET RQ DQ CLK/2 (Internal)
Input Data A
Input Latch A MUX Latch DAC Analog out
Input Data B
Input Latch B
tPD (B) Tpw1 Tpw0 CLK RESET (Active High) CLK/2 (Internal) ts Input Data A Input Data B N-2 N-1 N N+1 th N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 ts-rst th-rst (Active High) (Active Low) D-FF out 0 1 2 3 tPD (A)
tdo N+2 N+3 N+4
N+5
N
N+1 tdo
In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal.
- 24 -
CXA3197R
Block Diagram & Timing Chart (MUX.2 Mode)
CLK RQ DIV2IN DQ CLK/2 (Internal)
Input Data A
Input Latch A
Latch MUX Latch DAC Analog out
Input Data B
Input Latch B
Latch
tPD (B) Tpw1 Tpw0 CLK ts-DIV th-DIV DIV2IN ts Input Data A Input Data B N-2 N th N+2 N+4 N+6 N+8 0 1 2 3 tPD (A)
N-1
N +1
N+3
N+5
N+7
N+9
tdo N N+1 tdo
N+2
N+3
N+4
N+5
In MUX.2 mode, the 1/2 frequency-divided clock signal (DIV2IN) and Data A and Data B, which are synchronized with DIV2IN, are provided simultaneously. These signals are internally multiplexed and the resulting signal can be analog output.
- 25 -
CXA3197R
Block Diagram & Timing Chart (SELE.A, SELE.B Mode)
CLK
C2
Latch
Input Data A
Input Latch A Select Latch DAC Analog out
Input Data B
Input Latch B
Tpw1 CLK
Tpw0
tPD (A)
tPD (B)
0 C2 ts Input Data A N-2 N th N+2
1
th-C2
0 ts-C2
1
N+4
N+6
N+8
Input Data B
N-1
N +1
N+3
N+5
N+7
N+9
C2 Latch OUT
SELE. A
SELE. B
tdo tdo N-4 N-2 N N+2 N+5
N+7
In SELE.A and SELE.B modes, input Data A or Data B is selected and the selected data can be analog output. When C1 = 1 and C3 = 0, Data A is selected for C2 = 0, and Data B is selected for C2 = 1.
- 26 -
CXA3197R
Application Circuit The circuit shown below is the basic circuit when the analog output is terminated with external resistance of 50 for operation with dual 5V power supply in MUX.2 mode. The analog output uses AVCCO as the reference. The analog output full-scale voltage VFS is obtained with the following equation. VFS = VSET 63 x (15 + )xR 375 64 R = RO//RL RO: Output impedance (= 50) RL: External termination resistance
Here, VSET =
R2 VREF R1 + R2 (VREF 1.2V) (R1 + R2 1.2k)
+5V(D)
0V(D)
-5V(A)
0V(A) 48 47 46 45 44 43 42 41 40 39 38 37
(MSB) DA9
DA8
DA7
DVCC1
DA6
INV
PS
DGND1
R POLARITY
AGND2
NC
VOCLP
1 DA0 to DA9 RAM * Latch * etc DB0 to DB9
DA5
AVCC2 36 VSET 35 VREF 34 AGND2 33 AOUTP 32 AOUTN 31 AVCCO 30 DVCC2 29 C3 28 C2 27 C1 26 RL R1
0V(A) R2 -5V(A) -5V(A) 0V(A)
2 DA4 3 4 DA3 DA2
5 DA1 6 DA0 (LSB)
0V(A) 0V(A) 0V(D) RL 0V(A) -5V(D)
7 DB9 (MSB) 8 9 DB8 DB7
10 DB6 11 DB5
DB0 (LSB)
RESETP/E
RESETN/E
DIV2OUT
13 14 15 16 17 18 19 20 21 22 23 24
DB2
+5V(D)
82
CLKP/E
DB1
CLKN/E
130 0V(D)
TTL CLK/2 PECL CLK VBB
82
130
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 27 -
RESET/T
12 DB4
DGND2 25
DIV2IN
DB3
CLK/T
CXA3197R
Notes on Use * The CXA3197R has PECL and TTL input pins for the clock and reset inputs. When the clock is input at PECL level, it is recommended to also input the reset signal at PECL level. Likewise, when the clock is input at TTL level, it is recommended to also input the reset signal at TTL level. * The input signal impedance should be properly matched to ensure the stable CXA3197R operation at high speed. Particularly when ringing appears in the input clock in the MUX.1A and MUX.1B modes, if this ringing exceeds the clock input threshold value, the internal 1/2 frequency divider circuit may misoperate. * All TTL input pins of the CXA3197R except for the PS pin go to High level when left open, and only the PS pin goes to Low level when left open. Set the PS pin to High level to operate the IC. When the PECL input pins are left open, the P (positive) side goes to High level and the N (negative) side goes to Low level. The PECL input pins are complementary, so be sure to use the P and N sides together. * When the clock and reset input signal level is TTL, /T pins should be used and /E pins left open. When the clock and reset input signal level is PECL, /E pins should be used and /T pins left open. * The power supply and grounding have a profound influence on converter characteristics. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. -- The ground pattern should be as wide as possible. It is recommended to make the power supply and ground wider at an inner layer using a multi-layer board. To prevent a DC offset from being generated between the analog and digital power supply patterns, it is recommended to connect the patterns at one point via a ferrite-bead filter, etc. -- When using the CXA3197R with a single power supply, connect DGND1 and DGND2 to a common digital ground, and AGND2 to an analog ground. Also, DVCC1 and DVCC2 should use a common digital power supply, and AVCC2 should be connected to an analog power supply. AVCCO serves as the analog output reference, so while it does not need to share the analog power supply, it should be used within the range that satisfies the analog output compliance voltage. -- When using the CXA3197R with dual power supply, connect DGND1 and DVCC2 to the digital ground, and AVCC2 to the analog ground. DVCC1 uses a positive digital power supply (+5V, typ.), DGND2 uses a negative digital power supply (-5V, typ.), and AGND2 uses a negative analog power supply (-5V, typ.). Like when using a single power supply, the AVCCO pin can be used within the range that satisfies the analog output compliance voltage. However, connecting it to the analog ground and using the analog ground as the reference for the analog output is recommended. -- Ground the power supply pins as close to each pin as possible with a 0.1F or more ceramic chip capacitor. When using a single power supply, connect DVCC1 and DVCC2 to the digital ground, and AVCC2 and AVCCO to the analog ground. When using dual power supply, connect DVCC1 and DGND2 to the digital ground, and AGND2 to the analog ground. In this case, when using AVCCO within the range that satisfies the compliance voltage, be sure to also connect the AVCCO pin to the analog ground using a ceramic chip capacitor. * The CXA3197R is designed with an analog output impedance of 50. The analog outputs are wired with a characteristic impedance of 50, and waveforms free of reflection can be obtained by terminating the analog outputs with 50. Even when using only one of either AOUTP or AOUTN, if one analog output is terminated with 50, be sure to also terminate the other analog output with 50. (See the Application Circuit.) - 28 -
CXA3197R
Example of Representative Characteristics
Output full-scale voltage vs. VSET pin voltage
1100
Output full-scale voltage vs. Ambient temperature
1100 RL = 50 VSET = AGND2 + 937.5mW 1050
1000
VFS - Output full-scale voltage [mV]
Output full-scale voltage [mV]
900 RL = 50 800
1000
950
700 0.65 0.84 VSET pin voltage [V] 1.03 900 -25 0 25 50 75
Ta - Ambient temperature [C]
VREF pin voltage vs. Ambient temperature
Output zero offset voltage vs. Ambient temperature
7 RL = 50 VSET = AGND2 + 937.5mW 6
1280
1260
VOF - Output zero offset voltage [mV]
VREF pin voltage [mV]
5
1240
4
1220
3 -25 0 25 50 75
-25
0
25
50
75
Ta - Ambient temperature [C]
Ta - Ambient temperature [C]
Multiplying bandwidth
0
Analog output amplitude [dB]
-3
1
10 VSET pin input frequency [MHz]
100
- 29 -
CXA3197R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24
(8.0)
A 48 1 0.5 0.08 + 0.08 0.18 - 0.03 0.1 0.1 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 30 -
0.5 0.2

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